1. Field of the Invention
The present invention relates to a semiconductor device, a method of fabricating the semiconductor device, and a data processing system.
Priority is claimed on Japanese Patent Application No. 2010-249049, filed Nov. 5, 2010, the content of which is incorporated herein by reference.
2. Description of the Related Art
With high integration of semiconductor devices, miniaturization of MOS transistors has progressed. In semiconductor devices having memory cell regions, e.g., dynamic random access memories (DRAMs), it is necessary to dispose MOS transistors in the memory cell regions with high density. As a structure of the MOS transistor appropriate to miniaturization and high density arrangement, technology in which a gate electrode is buried within a lower portion of a trench (groove) disposed in a semiconductor substrate, and an insulating film is covered within an upper portion of the trench has been disclosed in Japanese Patent Application Laid-Open No. 2008-300843.
As technology corresponding to high density arrangement of MOS transistors, technology in which an insulating film is formed on an inner wall of a contact hole in a sidewall shape has been disclosed in Japanese Patent Application Laid-Open No. 2003-060028.